HD6432670 Hitachi, HD6432670 Datasheet - Page 134

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Bit
7
6
5
4
3
2 to 0
5.3.2
IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt
Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7
in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding
interrupt. IPR should be read in word size.
Rev. 2.0, 04/02, page 88 of 906
Bit Name
INTM1
INTM0
NMIEG
Interrupt Priority Registers A to K (IPRA to IPRK)
Initial Value
0
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
Interrupt Control Select Mode 1 and 0
These bits select either of two interrupt control
modes for the interrupt controller.
00: Interrupt control mode 0
Interrupts are controlled by I bit.
01: Setting prohibited.
10: Interrupt control mode 2
Interrupts are controlled by bits I2 to I0, and
IPR.
11: Setting prohibited.
NMI Edge Select
Selects the input edge for the NMI pin.
0: Interrupt request generated at falling edge of
NMI input
1: Interrupt request generated at rising edge of
NMI input
Reserved
These bits can be read from or written to.
However, the write value should always be 0.

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