HD6432670 Hitachi, HD6432670 Datasheet - Page 758

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
16.3.1
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD (H8S/2678 Series) and
eight 16-bit read-only ADDR registers, ADDRA to ADDRH (H8S/2678R Series), used to store
the results of A/D conversion. The ADDR registers, which store a conversion result for each
channel, are shown in table 16.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units.
In the H8S/2678 Series, the data bus between the CPU and the A/D converter is 8-bit width. The
upper byte can be read directly from the CPU, but the lower byte should be read via a temporary
register. The temporary register contents are transferred from the ADDR when the upper byte data
is read. When reading the ADDR, read the only upper byte, or read in word unit.
In the H8S/2678R Series, the data bus between the CPU and the A/D converter is 16-bit width.
The data can be read directly from the CPU.
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Group 0
(CH2 = 0)
AN0
AN1
AN2
AN3
Rev. 2.0, 04/02, page 712 of 906
A/D data register H (ADDRH)
A/D control/status register (ADCSR)
A/D control register (ADCR)
H8S/2678 Series
Channel Set 0 (CH3 = 1)
A/D Data Registers A to H (ADDRA to ADDRH)
Group 1
(CH2 = 1)
AN4
AN5
AN6
AN7
Analog Input Channel
Group 0
(CH2 = 0)
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Channel Set 1 (CH3 = 0)
Group 1
(CH2 = 1)
AN12
AN13
AN14
AN15
A/D Data Register
which stores
conversion result
ADDRA
ADDRB
ADDRC
ADDRD

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