HD6432670 Hitachi, HD6432670 Datasheet - Page 180

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.3.7
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of :$,7 pin input.
Bit
15
14
13
12
11
Rev. 2.0, 04/02, page 134 of 906
Bit Name
BRLE
BREQOE
IDLC
ICIS1
Bus Control Register (BCR)
Initial Value
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Description
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
%5(4
as I/O ports
1: External bus release enabled
%5(42
Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal
bus master performs an external address space
access, or when a refresh request is generated.
0:
%5(42
1:
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Idle Cycle State Number Select
Specifies the number of states in the idle cycle
set by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
Idle Cycle Insert 1
When consecutive external read cycles are
performed in different areas, an idle cycle can
be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
%5(42
%5(42
,
%$&.
Pin Enable
pin can be used as I/O port
output disabled
output enabled
, and
%5(42
pins can be used