HD6432670 Hitachi, HD6432670 Datasheet - Page 650

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Table 13.2 Clock Input to TCNT and Count Condition
Channel
TMR_0
TMR_1
All
Note: If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
13.3.5
TCSR displays status flags, and controls compare match output.
TCSR_0
Bit
7
Rev. 2.0, 04/02, page 604 of 906
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting.
Bit Name
CMFB
Timer Control/Status Register (TCSR)
Bit 2
CKS2
0
1
0
1
1
TCR
Bit 1
CKS1
0
1
0
0
1
0
0
1
1
Initial Value
0
Bit 0
CKS0
0
1
0
1
0
0
1
0
1
0
1
0
1
R/W
R/(W)*
Description
Clock input disabled
Internal clock, counted at falling edge of ø/8
Internal clock, counted at falling edge of ø/64
Internal clock, counted at falling edge of ø/8192
Count at TCNT_1 overflow signal*
Clock input disabled
Internal clock, counted at falling edge of ø/8
Internal clock, counted at falling edge of ø/64
Internal clock, counted at falling edge of ø/8192
Count at TCNT_0 compare match A*
External clock, counted at rising edge
External clock, counted at falling edge
External clock, counted at both rising and falling edges
Description
Compare Match Flag B
[Setting condition]
[Clearing conditions]
Set when TCNT matches TCORB
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
When DTC is activated by CMIB interrupt
while DISEL bit of MRB in DTC is 0