HD6432670 Hitachi, HD6432670 Datasheet - Page 389

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit
7
6
5
Bit Name
DAT1
DAT0
DARIE
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Destination Address Update Mode
These bits specify incrementing/decrementing
of the transfer destination address (EDDAR).
When an external device with DACK is
designated as the transfer destination in single
address mode, the specification by these bits is
ignored.
0X: Fixed
10: Incremented (+1 in byte transfer, +2 in word
transfer)
11: Decremented (–1 in byte transfer, –2 in
word transfer)
Destination Address Repeat Interrupt Enable
When this bit is set to 1, in the event of
destination address repeat area overflow the
IRF bit is set to 1 and the EDA bit cleared to 0 in
EDMDR, and transfer is terminated. If the EDIE
bit in EDMDR is 1 when the IRF bit in EDMDR
is set to 1, an interrupt request is sent to the
CPU. When used together with block transfer
mode, a destination address repeat interrupt is
requested at the end of a block-size transfer. If
the EDA bit is set to 1 in EDMDR for the
channel on which transfer is terminated by a
destination address repeat interrupt, transfer
can be resumed from the state in which it
ended. If a destination address repeat area has
not been designated, this bit is ignored.
0: Destination address repeat interrupt is not
requested
1: When destination address repeat area
overflow occurs, the IRF bit in EDMDR is set to
1 and an interrupt is requested
Rev. 2.0, 04/02, page 343 of 906