HD6432670 Hitachi, HD6432670 Datasheet - Page 767

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the
16.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (t
conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 indicates the A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in tables 16.3.
In scan mode, the values given in tables 16.3 apply to the first conversion time. The values given
in tables 16.4 apply to the second and subsequent conversions. The conversion time must be
within the ranges indicated in the descriptions, A/D Conversion Characteristics in section 24,
Electrical Characteristics. Therefore the CKS and CKS1 bits (H8S/2678 Series) or CKS1 and
CKS0 bits (H8S/2678R Series) must be set to satisfy this condition.
SPL
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
). The length of t
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total
D
) passes after the ADST bit is set to 1, then starts
CONV
) includes t
Rev. 2.0, 04/02, page 721 of 906
D
and the input sampling time