HD6432670 Hitachi, HD6432670 Datasheet - Page 161

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
If the same interrupt is selected as the DMAC activation factor and as the DTC activation factor or
CPU interrupt factor, these operate independently.
Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTA bit of DMAC's DMABCR, the DTCE bit of DTC's DTCERA to DTCERH, and the
DISEL bit of DTC's MRB.
Table 5.6
Settings
DMAC
DTA
0
1
Legend
Note: The SCI or A/D converter interrupt source is cleared when the DMAC or DTC reads or
X : The relevant interrupt cannot be used.
* :
: The relevant interrupt is used. Interrupt source clearing is performed.
: The relevant interrupt is used. The interrupt source is not cleared.
(The CPU should clear the source flag in the interrupt handling routine.)
Don’t care
writes to the prescribed register, and is not dependent upon the DTA bit or DISEL bit.
Interrupt Source Selection and Clearing Control
DTC
DTCE
0
1
*
DISEL
*
0
1
*
Interrupt Sources Selection/Clearing Control
DMAC
Rev. 2.0, 04/02, page 115 of 906
DTC
X
X
CPU
X
X

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