HD6432670 Hitachi, HD6432670 Datasheet - Page 183

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit
12
11
10
9
8
Bit Name
CAST
RMTS2
RMTS1
RMTS0
Initial Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Column Address Output Cycle Number Select
Selects whether the column address output
cycle in DRAM access comprises 3 states or 2
states. The setting of this bit applies to all areas
designated as DRAM space.
0: 2 states
1: 3 states
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
DRAM/Continuous Synchronous DRAM Space
Select
These bits designate DRAM/continuous
synchronous DRAM space for areas 2 to 5.
When continuous DRAM space is set, it is
possible to connect large-capacity DRAM
exceeding 2 Mbytes per area. In this case, the
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When continuous synchronous DRAM space is
set, it is possible to connect large-capacity
synchronous DRAM exceeding 2 Mbytes per
area. In this case, the
signals are output from
pins, respectively. When synchronous DRAM
mode is set, the mode registers of the
synchronous DRAM can be set.
000: Normal space
001: Normal space in areas 3 to 5
DRAM space in area 2
010: Normal space in areas 4 and 5
DRAM space in areas 2 and 3
011: DRAM space in areas 2 to 5
100: Continuous synchronous DRAM space
(setting prohibited in the H8S/2678 Series)
101: Synchronous DRAM mode setting (setting
prohibited in the H8S/2678 Series)
110: Setting prohibited
111: Continuous DRAM space in areas 2 to 5
signal is output from the
Rev. 2.0, 04/02, page 137 of 906
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