HD6432670 Hitachi, HD6432670 Datasheet - Page 24

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HD6432670

Manufacturer Part Number
HD6432670
Description
(HD64F267x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
19.10 Programmer Mode ....................................................................................................... 767
19.11 Power-Down States for Flash Memory ......................................................................... 767
19.12 Usage Notes................................................................................................................. 767
19.13 Note on Switching from F-ZTAT Version to Masked ROM Version............................. 773
Section 20 Masked ROM............................................................................... 775
Section 21 Clock Pulse Generator.................................................................. 777
21.1 Register Descriptions ................................................................................................... 777
21.2 Oscillator..................................................................................................................... 779
21.3 PLL Circuit.................................................................................................................. 782
21.4 Frequency Divider ....................................................................................................... 783
21.5 Usage Notes................................................................................................................. 783
Section 22 Power-Down Modes..................................................................... 785
22.1 Register Descriptions ................................................................................................... 788
22.2 Operation..................................................................................................................... 791
22.3 ø Clock Output Control ................................................................................................ 796
22.4 Usage Notes................................................................................................................. 797
Rev. 2.0, 04/02, page xxii of xliv
19.9.2 Software Protection ......................................................................................... 766
19.9.3 Error Protection............................................................................................... 766
21.1.1 System Clock Control Register (SCKCR) ........................................................ 777
21.1.2 PLL Control Register (PLLCR) ....................................................................... 779
21.2.1 Connecting a Crystal Resonator ....................................................................... 780
21.2.2 External Clock Input........................................................................................ 781
21.5.1 Notes on Clock Pulse Generator....................................................................... 783
21.5.2 Notes on Resonator ......................................................................................... 783
21.5.3 Notes on Board Design.................................................................................... 784
22.1.1 Standby Control Register (SBYCR) ................................................................. 788
22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................. 790
22.2.1 Clock Division Mode....................................................................................... 791
22.2.2 Sleep Mode ..................................................................................................... 791
22.2.3 Software Standby Mode................................................................................... 792
22.2.4 Hardware Standby Mode ................................................................................. 794
22.2.5 Module Stop Mode .......................................................................................... 795
22.2.6 All-Module-Clocks-Stop Mode........................................................................ 796
22.4.1 I/O Port Status................................................................................................. 797
22.4.2 Current Dissipation during Oscillation Stabilization Standby Period................. 797
22.4.3 EXDMAC/DMAC/DTC Module Stop ............................................................. 797
22.4.4 On-Chip Peripheral Module Interrupts ............................................................. 797
22.4.5 Writing to MSTPCR........................................................................................ 797

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