HD6432670 Hitachi, HD6432670 Datasheet - Page 242

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.7.2
With continuous synchronous DRAM space, the row address and column address are multiplexed.
In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to
MXC0 in DRAMCR. The address-precharge-setting command (Prechrge-sel) can be output on the
upper column address. Table 6.8 shows the relation between the settings of MXC2 to MXC0 and
the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used.
Table 6.8
Row
address
Column
address
X: Don’t care.
P: Precharge-sel
Rev. 2.0, 04/02, page 196 of 906
MXC2 MXC1 MXC0
0
1
0
1
Address Multiplexing
DRAMCR
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
x
0
1
x
0
1
x
0
1
0
1
x
0
1
0
1
Shift
Size
8 bits
9 bits
10 bits A23 to
11 bits A23 to
—
—
—
—
A23 to
A16
A23 to
A16
A23 to
A16
A16
A16
A23 to
A16
A23 to
A16
A23 to
A16
A23 to
A16
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Reserved (setting prohibited)
Reserved (setting prohibited)
P
P
P
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
P
P
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Pins
P
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0