HD6432670 Hitachi, HD6432670 Datasheet - Page 257

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

DQM has the 2-cycle latency when synchronous DRAM is read. Therefore, the DQM signal
cannot be specified to the Tc2 cycle data output if Tc1 cycle is performed for second or following
column address when the CAS latency is set to 1 to issue the READ command. Do not set the BE
bit to 1 when synchronous DRAM of CAS latency 1 is connected.
Burst Access Operation Timing: Figure 6.52 shows the operation timing for burst access. When
there are consecutive access cycles for continuous synchronous DRAM space, the column address
output cycles continue as long as the row address is the same for consecutive access cycles. The
row address used for the comparison is set with bits MXC2 to MXC0 in DRAMCR.
Rev. 2.0, 04/02, page 211 of 906