HD6432670 Hitachi, HD6432670 Datasheet - Page 939

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Item
1.1 Features
3.4 Memory Map in Each
Operating Mode
5.3.1 Interrupt Control
Register (INTCR)
Bits 7 to 6
5.3.1 Interrupt Control
Register (INTCR)
Bits 2 to 0
5.7.6 Note on IRQ Status
Register (ISR)
6.3.7 Bus Control
Register (BCR)
6.3.7 Bus Control
Register (BCR)
6.3.8 DRAM Control
Register (DRAMCR)
6.3.9 DRAM Access
Control Register
(DRACCR)
Figure 6.5 CAS Latency
Control Cycle Disable
Timing during Continuous
Synchronous DRAM
Space Write Access (for
CAS Latency 2)
6.3.10 Refresh Control
Register (REFCR)
Main Revisions and Additions in this Edition
Page
1
65
88
88
118
134
134
136
143 to
145
146
148
Revisions (See Manual for Details)
The following product deleted.
Model: HD64F2677R
Address map for H8S/2677R deleted.
Section 5.7.6 added.
Description changed.
Bit 15: External Bus Release Enable
Description changed.
Bit 13: This bit can be read from or written to. However, the
write value should always be 0.
Descriptions changed.
Bits 13, 11, 3: This bit can be read from or written to.
However, the write value should always be 0.
Descriptions changed.
H8S/2678 Series
Bit 6: This bit can be read from or written to. However, the
write value should always be 0.
H8S/2678R Series
Bits 14, 10, 7 to 4, 2: This bit (These bits) can be read from or
written to. However, the write value should always be 0.
Error in figure 6.5 corrected.
(Error)
Description changed.
Bit 11: This bit can be read from or written to. However, the
write value should always be 0.
Bit
7
6
Bit
2 to
0
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
Description
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
,
(Correction) DQMU, DQML
Rev. 2.0, 04/02, page 893 of 906