HD6432670 Hitachi, HD6432670 Datasheet - Page 279

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

In burst access in RAS down mode, the settings of bits ICIS2*, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. The timing in this case is illustrated in figures 6.70 and 6.71.
Address bus
Address bus
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
Data bus
Data bus
,
,
Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode
Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode
ø
ø
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
T
T
p
p
DRAM space read
DRAM space read
T
T
r
r
T
T
c1
c1
T
T
c2
c2
T
T
1
1
External read
External read
T
T
2
2
T
T
3
3
Rev. 2.0, 04/02, page 233 of 906
Idle cycle
Idle cycle
DRAM space write
DRAM space read
T
T
i
i
T
T
c1
c1
T
T
c2
c2