HD6432670 Hitachi, HD6432670 Datasheet - Page 100

• Manufacturer Part Number: HD6432670
• Description: (HD64F267x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

2.8
The H8S/2600 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.
Rev. 2.0, 04/02, page 54 of 906
Reset State
The CPU and on-chip peripheral modules are all initialized and stop. When the
low, all current processing stops and the CPU enters the reset state. All interrupts are masked
in the reset state. Reset exception handling starts when the
high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
Program Execution State
In this state the CPU executes program instructions in sequence.
Bus-Released State
In a product which has a bus master other than the CPU, such as a direct memory access
controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when
the bus has been released in response to a bus request from a bus master other than the CPU.
While the bus is released, the CPU halts operations.
Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further
details, refer to section 22, Power-Down Modes.
Processing States
# $
signal changes from low to
# $
input goes