HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 48

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory, data is loaded into to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption
during branching is reduced by first executing the instruction that follows the branch instruction,
and then branching. See the SH-1/SH-2/SH-DSP Software Manual for details.
Table 2.3
SH7000 Series CPU
BRA
ADD
Multiplication/Accumulation Operation: The five-stage pipeline system and the on-chip
multiplier enable 16-bit
16-bit
cycles.
T bit: T bit (in the status register) is set according to the result of a comparison, and in turn is the
condition (True/False) that determines if the program will branch. The T bit in the status register is
only changed by selected instructions, thus improving the processing speed.
Table 2.4
SH7000 Series CPU
CMP/GE
BT
BF
ADD
TST
BT
Immediate Data: Byte (8-bit) immediate data is located in the instruction code. Word or
longword immediate data is not located in instruction codes but is stored in a memory table. The
memory table is accessed by an immediate data transfer instruction (MOV) using the PC relative
addressing mode with displacement.
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REJ09B0272-0700
TRGET0
TRGET1
#–1,R0
R0,R0
TRGET
16-bit + 42-bit
TRGET
R1,R0
Delayed Branch Instructions
T Bit
R1,R0
16-bit
42-bit multiplication/accumulation operations can be executed in 2–3
Description
T bit is set when R0 ≥ R1. The program
branches to TRGET0 when R0 ≥ R1
and to TRGET1 when R0<R1.
T bit is not changed by ADD. T bit is set
when R0 = 0. The program branches if
R0 = 0.
Description
Executes an ADD before
branching to TRGET.
32-bit multiplication operations to be executed in 1–3 cycles.
Conventional CPU
ADD.W
BRA
Conventional CPU
CMP.W
BGE
BLT
SUB.W #1,R0
BEQ
TRGET
TRGET0
TRGET1
TRGET
R1,R0
R1,R0