HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 235

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

DREQ pin sampling timing in cycle-steal mode
In cycle-steal mode, the sampling timing is the same regardless of whether DREQ is detected
by edge or level. With edge detection, however, once the signal is sampled it will not be
sampled again until the next edge detection. Once DREQ input is detected, the next sampling
is not performed until the first state, among those DMAC bus cycles thereby produced, in
which a DACK signal is output (including the detection state itself). The next sampling occurs
immediately prior to the rising edge of the clock pulse (CK) of the third state after the bus
cycle previous to the bus cycle in which the DACK signal is output.
Figures 9.13 to 9.22 show the sampling timing of the DREQ pin in cycle-steal mode for each
bus cycle. When no DREQ input is detected at the sampling after the aforementioned DREQ
detection, the next sampling occurs in the next state in which a DACK signal is output. If no
DREQ input is detected at this time, sampling occurs at every subsequent state.
Figure 9.13 DREQ
Bus cycle
DREQ
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 1 State)
DACK
CK
DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
CPU
CPU
CPU
Section 9 Direct Memory Access Controller (DMAC)
DMAC
Rev. 7.00 Jan 31, 2006 page 209 of 658
CPU
CPU
CPU
REJ09B0272-0700
DREQ
DREQ
DREQ Level
CPU