HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 39

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

16-bit
integrated
timer pulse
unit (ITU)
Type
Bus control
(cont)
DMAC
Symbol
WAIT
RAS
CASH
CASL
RD
WRH
WRL
CS0–
CS7
AH
HBS,
LBS
WR
DREQ0,
DREQ1
DACK0,
DACK1
TIOCA0,
TIOCB0
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3
Pin No.
(PRQP0112
JA-A)
56
54
49
51
59
58
57
48–51,
53–56
63
23, 58
57
67, 69
66, 68
53, 55
64, 65
97, 98
100, 101
Pin No.
(PTQP0120
LA-A)
59
57
52
54
64
63
62
51–54,
56–59
68
24, 63
62
72, 74
71, 73
56, 58
69, 70
103, 105
107, 108
I/O Name and Function
I
O
O
O
O
O
O
O
O
O
O
I
O
I/O ITU input capture/output compare (channel 0):
I/O ITU input capture/output compare (channel 1):
I/O ITU input capture/output compare (channel 2):
I/O ITU input capture/output compare (channel 3):
Wait: Requests the insertion of wait states
(T
address space is accessed.
Row address strobe: DRAM row-address
strobe timing signal.
Column address strobe high: DRAM column-
address strobe timing signal. Output to
access the upper eight data bits.
Column address strobe low: DRAM column-
address strobe timing. Output to access the
lower eight data bits.
Read: Indicates reading of data from an
external device.
Upper write: Indicates write access to the
upper eight bits of an external device.
Lower write: Indicates write access to the
lower eight bits of an external device.
Chip select 0–7: Chip select signals for
accessing external memory and devices.
Address hold: Address hold timing signal for a
device using a multiplexed address/data bus.
Upper/lower byte strobe: Upper and lower
byte strobe signals. (Also used as WRH and
A0.)
Write: Brought low during write access. (Also
used as WRL.)
DMA transfer request (channels 0 and 1):
Input pins for external DMA transfer requests.
DMA transfer acknowledge (channels 0 and
1): Indicates that DMA transfer is
acknowledged.
Input capture or output compare pins.
Input capture or output compare pins.
Input capture or output compare pins.
Input capture or output compare pins.
W
) into the bus cycle when the external
Rev. 7.00 Jan 31, 2006 page 13 of 658
Section 1 Overview
REJ09B0272-0700