HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 183

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HD6417034B

Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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AD15–
A21–
access to the DRAM area. When the row address for the next DRAM access is the same as the
previous DRAM access, burst operation continues. Figure 8.27 shows the timing of RAS down
mode when external memory space is accessed during burst operation.
The RAS signal can be held low in the DRAM for a limited time; the RAS signal must be
returned to high within the specified limits even when RAS down mode is selected since the
critical low level period is set. In this chip, even when RAS down mode is selected, the RAS
signal automatically reverts to high when the DRAM is refreshed, so the BSC’s refresh control
function can be employed to set a CAS-before-RAS refresh that will keep operation within
specifications. See section 8.5.6, Refresh Control, for details.
RAS
CAS
AD0
WR
CK
A0
T
p
Row address
T r
DRAM access
address 1
Column
Figure 8.27 RAS Down Mode
T
c
Data 1
address 2
Column
T
c
External memory
Data 2
space access
External
memory
Rev. 7.00 Jan 31, 2006 page 157 of 658
memory data
T1
Section 8 Bus State Controller (BSC)
External
address 3
Column
DRAM access
T
c
Data 3
address 4
Column
REJ09B0272-0700
T
c
Data 4

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