HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 138

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Bus State Controller (BSC)
7) finish in 1 state, regardless of the settings of bits RW0 and RW7. The WAIT signal is not
sampled for either.
Table 8.4 summarizes read cycle state information.
Table 8.4
Notes: 1. Sampled in the address/data multiplexed I/O space
Bits 7–2—Reserved: These bits are always read as 1. The write value should always be 1.
Bit 1—Wait State Control During Write (WW1): WW1 determines the number of states in
write cycles for the DRAM space (area 1) and whether or not to sample the WAIT signal. When
the DRAM enable bit (DRAME) in BCR is set to 1 and area 1 is being used as DRAM space,
clearing WW1 to 0 makes the column address output cycle finish in 1 state (short pitch). When
WW1 is set to 1, it finishes in 2 states plus the wait states from the WAIT signal (long pitch).
Note: Write 0 to WW1 only when area 1 is used as DRAM space (DRAME bit in BCR is 1).
Bit 1: WW1
0
1
Rev. 7.00 Jan 31, 2006 page 112 of 658
REJ09B0272-0700
Bits 15–8:
RW7–RW0
0
1
2. During a CBR refresh, the WAIT signal is ignored and the wait state from the RLW1 and
Never write 0 to WW1 when area 1 is used as external memory space (DRAME is 0).
RLW0 bits in RCR is inserted.
WAIT
WAIT Pin
Input
Signal
Not
sampled
during
read
cycle *
Sampled
during
read cycle
(Initial
value)
WAIT
WAIT
Read Cycle States
DRAM Space (DRAME = 1)
Column address cycle: 1 state (short pitch)
Column address cycle: 2 states + wait state
from WAIT (long pitch)
1
External Memory
Space
Areas 1, 3–5,7: 1
state, fixed
Areas 0, 2, 6: 1 state
+ long wait state
Areas 1, 3–5, 7: 2
states + wait states
from WAIT
Areas 0, 2, 6: 1 state
+ long wait state +
wait state from WAIT
External Memory Space
DRAM Space
Column add-
ress cycle: 1
state, fixed
(short pitch)
Column
address cycle:
2 states + wait
state from
WAIT (long
pitch) *
(Initial value)
Read Cycle States
2
Multi-
plexed
I/O
4 states
+ wait
states
from
WAIT
Area 1 External Memory Space
(DRAME = 0)
Setting inhibited
2 states + wait state from WAIT
On-Chip
Supporting
Modules
3 states,
fixed
Internal Space
On-Chip
ROM and
RAM
1 state,
fixed