HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 263

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 0—Timer Synchro 0 (SYNC0): SYNC0 selects synchronizing mode for channel 0.
Bit 0: SYNC0
0
1
10.2.3
The timer mode register (TMDR) is an eight-bit read/write register that selects PWM mode for
channels 0–4, sets phase counting mode for channel 2, and sets the conditions for the overflow
flag (OVF). TMDR is initialized to H'80 or H'00 by a reset and in standby mode.
Note: * Undefined
Bit 7—Reserved: Bit 7 is read as undefined. The write value should be 0 or 1.
Bit 6—Phase Counting Mode (MDF): MDF selects phase counting mode for channel 2.
Bit 6: MDF
0
1
When the MDF bit is set to 1 to select phase counting mode, the timer counter (TCNT2) becomes
an up/down-counter and the TCLKA and TCLKB pins become count clock input pins. TCNT2
counts on both the rising and falling edges of TCLKA and TCLKB, with increment/decrement
chosen as follows:
Count
Direction
TCLKA pin
TCLKB pin
Bit
Initial value
Read/Write
Timer Mode Register (TMDR)
Decrement
Rising
Low
Description
The timer counter for channel 0 (TCNT0) operates independently (Preset/clear
of TCNT0 is independent of other channels)
Channel 0 operates synchronously. Synchronized preset/clear of TNCT0
enabled.
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
—
—
7
*
High
Rising
MDF
R/W
6
0
Falling
High
FDIR
R/W
5
0
Low
Falling
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
PWM4
R/W
4
0
Increment
Rising
High
Rev. 7.00 Jan 31, 2006 page 237 of 658
PWM3
R/W
3
0
High
Falling
PWM2
R/W
2
0
Falling
Low
REJ09B0272-0700
PWM1
R/W
1
0
(Initial value)
(Initial value)
Low
Rising
PWM0
R/W
0
0