HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 425

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
4.
Transmitting and Receiving Data: SCI Initialization (Synchronous Mode): Before transmitting
or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then
initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
Figure 13.16 shows a sample flowchart for initializing the SCI.
Serial clock
Serial data
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source
is selected, the SCI outputs data in synchronization with the input clock. Data is output from
the TxD pin in order from the LSB (bit 0) to the MSB (bit 7).
data from TDR into TSR, transmits the MSB, then begins serial transmission of the next frame.
If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the
transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in
SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
After the end of serial transmission, the SCK pin is held in the high state.
TDRE
TEND
Transmit direction
request
TXI
Figure 13.15 Example of SCI Transmit Operation
Bit 0
LSB
clears TDRE to 0
data in TDR and
handler writes
TXI interrupt
Bit 1
1 frame
request
TXI
Section 13 Serial Communication Interface (SCI)
MSB
Bit 7
Rev. 7.00 Jan 31, 2006 page 399 of 658
Bit 0
Bit 1
REJ09B0272-0700
Bit 6
request
Bit 7
TEI