HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 193

no-image

HD6417034B

Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034BVFN20
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD6417034BVFN20
Manufacturer:
RENESAS
Quantity:
482
Part Number:
HD6417034BVFW20
Manufacturer:
MITSUBISHI
Quantity:
101
Part Number:
HD6417034BVXN20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 8.12 Bus Cycle States when Accessing Address Spaces
Note: * The number of long wait states (1 to 4) is set in WCR3.
Address Space
External memory (areas 1, 3–5, 7) 1 state fixed; WAIT signal
External memory (Areas 0, 2, 6;
long wait avail-able)
DRAM space (area 1)
Multiplexed I/O space (area 6)
On-chip supporting module space
(area 5)
On-chip ROM (area 0)
On-chip RAM (area 7)
Address Space
External memory (area 1)
External memory (areas 3–5, 7)
External memory (Areas
0, 2, 6; long wait available)
DRAM space (area 1)
Multiplexed I/O space (area 6)
On-chip peripheral module space
(area 5)
On-chip ROM (area 0)
On-chip RAM (area 7)
Corresponding Bits in
WCR1 and WCR2 = 0
ignored
1 state + long wait state * ,
WAIT signal ignored
Column address cycle:
1 state, WAIT signal ignored
(short pitch)
4 states + wait states from WAIT signal
3 states fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
WW1 of WCR1=0
Setting prohibited
2 states + wait states from WAIT signal
1 state + long wait state * + wait states from WAIT signal
Column address cycle:
1 state, WAIT signal
ignored (short pitch)
4 states + wait states from WAIT signal
3 states fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
CPU Write Cycle, DMAC Dual Mode Memory Write Cycle
CPU Read Cycle, DMAC Dual Mode Read Cycle, DMAC
Single Mode Memory Read/Write Cycle
Rev. 7.00 Jan 31, 2006 page 167 of 658
(WW1 of WCR1)
Section 8 Bus State Controller (BSC)
Corresponding Bits in
WCR1 and WCR2 = 1
2 states + wait states from
WAIT signal
1 state + long wait state * +
wait states from WAIT signal
Column address cycle:
2 states + wait states from
WAIT signal (long pitch)
WW1 of WCR1=1
2 states + wait state from
WAIT signal
Column address cycle:
2 states + wait states from
WAIT signal (long pitch)
REJ09B0272-0700

Related parts for HD6417034B