HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 237

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = 2 States + 1 Wait
Figure 9.16 DREQ
Figure 9.17 DREQ
Bus cycle
Bus cycle
Note: When DREQ is negated at the third state of the DMAC cycle, the next DMA
Note: Illustrates the case when DACK is output during the DMAC write cycle.
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = 2 States)
DREQ
DREQ
DACK
DACK
CK
CK
transfer will be executed because the sampling is performed at the second state
of the DMAC cycle.
DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ
CPU
CPU
CPU
CPU
CPU
CPU
Section 9 Direct Memory Access Controller (DMAC)
State)
DMAC (R) DMAC (W)
T1
DMAC
Tw
T2
Rev. 7.00 Jan 31, 2006 page 211 of 658
CPU
DMAC (W): DMAC write cycle
DMAC (R): DMAC read cycle
CPU
T1
DMAC
Tw
CPU
T2
REJ09B0272-0700
DREQ
DREQ
DREQ Level
DREQ
DREQ
DREQ Level
CPU
CPU