HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 168

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HD6417034B

Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 8 Bus State Controller (BSC)
Areas 0, 2, and 6 have long wait functions. When the corresponding bits in WCR1 and WCR2 are
cleared to 0, the access cycle is 1 state plus the number of long wait states (set in WCR3,
selectable between 1 and 4) and the WAIT pin input signal is not sampled. When the bits are set to
1, the WAIT signal is sampled and the number of states is 1 plus the number of long wait states
plus the number of wait states set by the WAIT signal. The WAIT signal is sampled at the rise of
the system clock (CK) directly preceding the last long wait state and the wait states are inserted as
long as the level is low. When a high level is detected, it shifts to the final long wait state. Figure
8.14 shows the wait state timing when accessing the external memory spaces of areas 0, 2, and 6.
Rev. 7.00 Jan 31, 2006 page 142 of 658
REJ09B0272-0700
Read
Write
Figure 8.13 Wait State Timing for External Memory Space Access (2 States Plus Wait
WRH, WRL
AD15–AD0
AD15–AD0
A21–A0
WAIT
CSn
RD
CK
T1
States from WAIT
Tw (wait state)
WAIT
WAIT
WAIT Signal)
T2

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