HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 344

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Programmable Timing Pattern Controller (TPC)
11.2.2
The port B data register (PBDR) is a 16-bit read/write register that stores output data for groups 0–
3 when TPC output is used. For details of PBDR, see section 16, I/O Ports.
Note: * Bits set to TPC output by NDERA or NDERB are read-only.
Note: * Bits set to TPC output by NDERA or NDERB are read-only.
11.2.3
NDRA is an eight-bit read/write register that stores the next output data for TPC output groups 1
and 0 (TP7–TP0). When used for TPC output, the contents of NDRA are transferred to the
corresponding PBDR bits when the ITU compare match specified in the TPC output control
register, TPCR, occurs.
The address of NDRA differs depending on whether TPCR settings select the same trigger or
different triggers for TPC output groups 1 and 0. NDRA is initialized to H'00 by a reset. It is not
initialized in standby mode.
Same Trigger for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by
the same compare match, the address of NDRA is H'FFFFF5. The upper 4 bits become group 1
and the lower 4 bits become group 0. Address H'5FFFFF7 in such cases consists entirely of
reserved bits. These bits cannot be modified and are always read as 1.
Address H'5FFFFF5
Bits 7–4—Next Data 7–4 (NDR7–NDR4): NDR7–NDR4 store the next output data for TPC
output group 1.
Rev. 7.00 Jan 31, 2006 page 318 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Port B Data Register (PBDR)
Next Data Register A (NDRA)
PB15DR PB14DR PB13DR PB12DR PB11DR PB10DR PB9DR
PB7DR
R/(W) *
R/(W) *
15
0
7
0
PB6DR
R/(W) *
R/(W) *
14
0
6
0
PB5DR
R/(W) *
R/(W) *
13
0
5
0
PB4DR
R/(W) *
R/(W) *
12
0
4
0
PB3DR
R/(W) *
R/(W) *
11
0
3
0
PB2DR
R/(W) *
R/(W) *
10
0
2
0
PB1DR
R/(W) *
R/(W) *
9
0
1
0
PB8DR
PB0DR
R/(W) *
R/(W) *
8
0
0
0