HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 346
HD6417034B
Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417034B.pdf
(687 pages)
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Section 11 Programmable Timing Pattern Controller (TPC)
Bits 3–0—Next Data 3–0 (NDR3–NDR0): NDR3–NDR0 store the next output data for TPC
output group 0.
11.2.4
NDRB is an eight-bit read/write register that stores the next output data for TPC output groups 3
and 2 (TP15–TP8). When used for TPC output, the contents of NDRB are transferred to the
corresponding PBDR bits when the ITU compare match specified in the TPC output control
register, TPCR, occurs.
The address of NDRB differs depending on whether TPCR settings select the same trigger or
different triggers for TPC output groups 3 and 2. NDRB is initialized to H'00 by a reset. It is not
initialized in standby mode.
Same Trigger for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by
the same compare match, the address of NDRB is H'FFFFF4. The upper 4 bits become group 3
and the lower 4 bits become group 2. Address H'5FFFFF6 consists entirely of reserved bits. These
bits are always read as 1, and the write value should always be 1.
Address H'5FFFFF4
Bits 7–4—Next Data 15–12 (NDR15–NDR12): NDR15–NDR12 store the next output data for
TPC output group 3.
Bits 3–0—Next Data 11–8 (NDR11–NDR8): NDR11–NDR8 store the next output data for TPC
output group 2.
Rev. 7.00 Jan 31, 2006 page 320 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Next Data Register B (NDRB)
NDR15
R/W
—
—
7
1
7
0
NDR14
R/W
—
—
6
1
6
0
NDR13
R/W
—
—
5
1
5
0
NDR12
R/W
—
—
4
1
4
0
NDR11
NDR3
R/W
R/W
3
0
3
0
NDR10
NDR2
R/W
R/W
2
0
2
0
NDR1
NDR9
R/W
R/W
1
0
1
0
NDR0
NDR8
R/W
R/W
0
0
0
0
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