HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 239

• Manufacturer Part Number: HD6417034B
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = DRAM Bus Cycle
Figure 9.20 DREQ
Figure 9.21 DREQ
Detection and DACK Active-Low) (Single Address Mode, Bus Cycle = Address/Data
Bus cycle
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA
Bus cycle
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA
DREQ
DACK
DREQ
DACK
CK
CK
transfer will be executed because the sampling is performed at the second state
of the DMAC cycle.
transfer will be executed because the sampling is performed at the second state
of the DMAC cycle.
DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ
DREQ
CPU
CPU
CPU
CPU
CPU
(Long Pitch Normal Mode))
Multiplex I/O Bus Cycle)
CPU
Tp
DMAC(R)
Tr
T1
Section 9 Direct Memory Access Controller (DMAC)
Tc
T2
DMAC
Tc
T3
DMAC
(W)
T4
Rev. 7.00 Jan 31, 2006 page 213 of 658
CPU
CPU
DMAC (W): DMAC write cycle
DMAC (R): DMAC read cycle
Tp
DMAC (R)
T1
Tr
Tc
T2
DMAC
Tc
T3
DMAC
(W)
T4
REJ09B0272-0700
DREQ
DREQ
DREQ Level
DREQ Level
DREQ
DREQ
CPU
CPU