HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 216
HD6417034B
Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417034B.pdf
(687 pages)
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Section 9 Direct Memory Access Controller (DMAC)
The DE bit is initialized to 0 by a reset and in standby mode.
Bit 0: DE
0
1
9.2.5
The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA
transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset and in
standby mode.
Note: * Write only 0 to clear the flag.
Bits 15–10—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 9 and 8—Priority Mode Bits 1 and 0 (PR1 and PR0): PR1 and PR0 select the priority level
between channels when there are simultaneous transfer requests for multiple channels.
Bit 9: PR1
0
0
1
1
Bits 7–3—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 7.00 Jan 31, 2006 page 190 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
DMA Operation Register (DMAOR)
Bit 8: PR0
0
1
0
1
Description
DMA transfer disabled
DMA transfer enabled
——
15
—
R
R
0
7
0
Fixed priority order (Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) (Initial value)
Fixed priority order (Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0)
Round-robin mode priority order (the priority order immediately after a
reset is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1)
External-pin round-robin mode priority order (the priority order
immediately after a reset is Ch. 3 > Ch. 2 > Ch. 1 > Ch. 0)
Description
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
11
—
—
R
R
0
3
0
R/(W) *
AE
10
—
R
0
2
0
R/(W) *
NMIF
PR1
R/W
9
0
1
0
(Initial value)
DME
PR0
R/W
R/W
8
0
0
0
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