HD6417034B RENESAS [Renesas Technology Corp], HD6417034B Datasheet - Page 199

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HD6417034B

Manufacturer Part Number
HD6417034B
Description
32-Bit RISC Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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The low width of RAS output may be shorter than usual in a reset (2.5 tcyc
preventing the specified value (t
There are no problems regarding operations except for the above conditions.
There are the following four cases (figures 8.38 to 8.41) for the output states of DRAM control
signals (RAS, CAS, and WR) corresponding to RES latch timing. Actual output levels are shown
by solid lines (not by dashed lines).
AD0–AD15
AD0–AD15
A0–A21
A0–A21
Corresponding DRAM conditions: Long-pitch/normal mode
RES
RAS
CAS
RES
RAS
CAS
WR
WR
CK
CK
RES latch
timing
Figure 8.38 Long-Pitch Mode Write (1)
Figure 8.39 Long-Pitch Mode Write (2)
RES latch
timing
RAS
Manual reset
) of DRAM from being satisfied.
Manual reset
Tp
Tp
Long-pitch/high-speed page mode
Row address
Row address
Data output
Tr
Tr
Rev. 7.00 Jan 31, 2006 page 173 of 658
Section 8 Bus State Controller (BSC)
Column address
FFFF
Tc1
Tc1
Data output
Tc2
Tc2
FFFF
1.5 tcyc),
REJ09B0272-0700

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