LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 8

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

FIGURES
FIGURE 1 − SERIAL DATA .........................................................................................................................................66
FIGURE 2 − KEYBOARD LATCH ..............................................................................................................................113
FIGURE 3 − MOUSE LATCH.....................................................................................................................................113
FIGURE 4 − GPIO FUNCTION ILLUSTRATION........................................................................................................119
FIGURE 5 − FAN TACHOMETER INPUT AND CLOCK SOURCE............................................................................125
FIGURE 6 − CONCEPTUAL BLOCK DIAGRAM OF FAN MONITORING LOGIC .....................................................126
FIGURE 7 − SAMPLE SMBUS SINGLE BYTE TRANSACTION ...............................................................................135
FIGURE 8 − REPRESENTATIVE DIAGRAM OF SMBUS AND SMBUS2 .................................................................135
FIGURE 9 − WRITE BYTE PROTOCOL....................................................................................................................136
FIGURE 10 − READ BYTE PROTOCOL ...................................................................................................................136
FIGURE 11 − LPC AND SMBUS I/O ACCESSES TO THE X-BUS INTERFACE (MODE 1/MODE 2) ......................145
FIGURE 12 − WAKEUP LOGIC .................................................................................................................................149
FIGURE 13 − POWER-UP TIMING ...........................................................................................................................185
FIGURE 14 − INPUT CLOCK TIMING .......................................................................................................................185
FIGURE 15 − OUTPUT CLOCK TIMING ...................................................................................................................185
FIGURE 16 − PCI CLOCK TIMING............................................................................................................................185
FIGURE 17 − RESET TIMING ...................................................................................................................................185
FIGURE 18 − OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS...................................................185
FIGURE 19 − INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.......................................................185
FIGURE 20 − I/O WRITE ...........................................................................................................................................185
FIGURE 21 − I/O READ.............................................................................................................................................185
FIGURE 22 − DMA REQUEST ASSERTION THROUGH LDRQ#.............................................................................185
FIGURE 23 − DMA WRITE (FIRST BYTE) ................................................................................................................185
FIGURE 24 − DMA READ (FIRST BYTE)..................................................................................................................185
FIGURE 25 − FLOPPY DISK DRIVE TIMING (AT MODE ONLY) .............................................................................185
FIGURE 26 − EPP 1.9 DATA OR ADDRESS WRITE CYCLE ...................................................................................185
FIGURE 27 − EPP 1.9 DATA OR ADDRESS READ CYCLE.....................................................................................185
FIGURE 28 − EPP 1.7 DATA OR ADDRESS WRITE CYCLE ...................................................................................185
FIGURE 29 − EPP 1.7 DATA OR ADDRESS READ CYCLE.....................................................................................185
FIGURE 30 − PARALLEL PORT FIFO TIMING .........................................................................................................185
FIGURE 31 − ECP PARALLEL PORT FORWARD TIMING ......................................................................................185
FIGURE 32 − ECP PARALLEL PORT REVERSE TIMING........................................................................................185
FIGURE 33 - IRDA RECEIVE TIMING.......................................................................................................................185
FIGURE 34 − IRDA TRANSMIT TIMING ...................................................................................................................185
FIGURE 35 − AMPLITUDE SHIFT KEYED IR RECEIVE TIMING .............................................................................185
FIGURE 36 − AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING ..........................................................................185
FIGURE 37 − SMBUS TIMING ..................................................................................................................................185
FIGURE 38 − X-BUS READ TIMING .........................................................................................................................185
FIGURE 39 − X-BUS WRITE TIMING........................................................................................................................185
FIGURE 40 − X-BUS AND LPC I/O READ CYCLE....................................................................................................185
FIGURE 41 − X-BUS AND LPC I/O WRITE CYCLE ..................................................................................................185
FIGURE 42 − SMBUS TO X-BUS WRITE CYCLE TIMING FOR LCD AND I/O CYCLES.........................................185
FIGURE 43 − SMBUS TO X-BUS READ CYCLE TIMING FOR LCD AND I/O CYCLES ..........................................185
FIGURE 44 − SETUP AND HOLD TIME....................................................................................................................185
FIGURE 45 − SERIAL PORT DATA ..........................................................................................................................185
FIGURE 46 − KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING .......................................................................185
FIGURE 47 − FAN OUTPUT TIMING ........................................................................................................................185
FIGURE 48 − FAN TACHOMTER INPUT TIMING.....................................................................................................185
FIGURE 49 − LED OUTPUT TIMING ........................................................................................................................185
FIGURE 50 – XNOR-CHAIN TEST STRUCTURE.....................................................................................................185
SMSC LPC47S45x
Page 8 of 259
Rev. 06-01-06
DATASHEET