LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 215

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

SMSC LPC47S45x
Base I/O Address 1 –
Low Byte (Note 1)
Default = 0x00
on VTR POR, VCC
POR, PCI Reset and
Soft Reset
Bit 1 is reset on
VCC POR, VTR POR
and PCI Reset
Base I/O Address 2 –
High Byte (Note 1)
Default = 0x00
on VTR POR, VCC
POR, PCI Reset and
Soft Reset
Base I/O Address 2 –
Low Byte (Note 1)
Default = 0x00
on VTR POR, VCC
POR, PCI Reset and
Soft Reset
Bit 1 is reset on
VCC POR, VTR POR
and PCI Reset
Base I/O Address 3 –
High Byte (Note 1)
Default = 0x00
on VTR POR, VCC
POR, PCI Reset and
Soft Reset
NAME
Table 93 − X-Bus, Logical Device 8 [Logical Device Number = 0x08]
R/W,
Read-Only
when the Base
I/O Address 1
– Low Byte
Register
bit[1]=1
R/W,
Read-Only
when the Base
I/O Address 2
– Low Byte
Register
bit[1]=1
R/W,
Read-Only
when the Base
I/O Address 2
– Low Byte
Register
bit[1]=1
R/W,
Read-Only
when the Base
I/O Address 3
– Low Byte
Register
bit[1]=1
REG INDEX
0x63
0x64
0x65
0x66
Register 0x63 sets the low byte of the base I/O address for chip
select 1. Bit 1 is the write protect bit for registers 62 and 63.
Bit 0 is the disable bit for XCS1.
Bits [7:2] =address[7:2]
Bit[1] = Register 62, 63 Write Protect. Cleared by VCC POR,
VTR POR and PCI Reset only. Cannot be cleared by software
writing to this bit.
0=Register 62 and 63 are read/write
1=Register 62 and 63 are read-only
Bit[0] = Disable bit for XCS1.
0=enable chip select
1=disable chip select
Register 0x64 sets the high byte of the base I/O address for
chip select 2.
Bits [7:0] =address[15:8]
Note: Bits[15:12] must be ‘0’ since the chip performs 16-bit
address qualification on the base I/O addresses.
Register 0x65 sets the low byte of the base I/O address for
chip select 2. Bit 1 is the write protect bit for registers 64 and
65. Bit 0 is the disable bit for nXCS2.
Mode 1:
Bits [7:2] =address[7:2]
Mode 2:
Bits [7:4] =address[7:4]
Bits [3:2] are reserved
Bit[1] = Register 64, 65 Write Protect. Cleared by VCC POR,
VTR POR and PCI Reset only. Cannot be cleared by software
writing to this bit.
0=Register 64 and 65 are read/write
1=Register 64 and 65 are read-only
Bit[0] = Disable bit for nXCS2.
0=enable chip select
1=disable chip select
Register 0x66 sets the high byte of the base I/O address for
chip select 3.
Bits [7:0] =address[15:8]
Note: Bits[15:12] must be ‘0’ since the chip performs 16-bit
address qualification on the base I/O addresses.
DATASHEET
Page 215 of 259
DEFINITION
Rev. 06-01-06
STATE