LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 154

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

7.5 System Management Interrupt (SMI)
The LPC47S45x implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable
interrupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output
consists of the enabled interrupts from Super I/O Device Interrupts and many of the GPIOs pins. The GP27/nIO_SMI
pin, when selected for the nIO_SMI function, can be programmed to be active high or active low via the polarity bit in
the GP27 register. The output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the
GP27 register. The nIO_SMI pin function defaults to active low, open-drain output.
The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 7. The nSMI output is then
enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be
enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2
An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows:
nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or (EN_FINT and
IRQ_FINT) or (EN_WDT and IRQ_WDT) or (EN_MINT and IRQ_MINT) or (EN_KINT and IRQ_KINT) or (EN_SMBus
and IRQ_SMBus) or (EN_RI1 and IRQ_RI1) or (EN_P12 and IRQ_P12) or (EN_RI2 and IRQ_RI2)
Note: The prefixes EN and IRQ are used above to indicate SMI enable bit and SMI status bit respectively.
7.5.1
SMI REGISTERS
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and Enable registers
3-5. The polarity of the edge used to set the status bit and generate an SMI is controlled by the polarity bit of the
control registers. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function
is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding SMI status bit.
Status bits for the GPIOs are cleared on a write of ‘1’.
The SMI logic for these events is implemented such that the output of the status bit for each event is combined with
the corresponding enable bit in order to generate an SMI.
The P12 and P16 bits enable an SMI event on single high-to-low edge or on both high-to-low and low-to-high edges.
Default is single edge. There is also a polarity select bit for P12 in the configuration register 0xF0 in logical device 7.
The register that selects the edge, Edge Select register, is located at the address programmed in the Base I/O
Address register in the Logical Device A at an offset of 21h. Refer also to PME Status and Enable register 2. See
the Runtime Registers sections for description on these registers.
If both edges are selected for generating an SMI via p16, then the SMI is asserted on each edge until the P16 SMI
status bit is cleared. If both edges are selected for generating an SMI via P12, then a short pulse (20ns) is generated
on each edge. However, the P12 SMI status bit is set on each edge until cleared. The P12 SMI is not recommended
to be used in this mode of operation.
Note that P12 and P16 bits are cleared by write of ‘1’. The SMI generated by P16 is deasserted when the P16 SMI
status bit is written to ‘1’. However, the SMI generated by P12 is cleared at the source.
The SMI logic for the P16 event is implemented such that the output of the status bit for the event is combined with
the corresponding enable bit in order to generate an SMI.
The SMI registers are accessed at an offset from Runtime Registers Block (see Runtime register section for more
information).
The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2. All of these
status bits are cleared at the source except for IRINT, which is cleared by a read of the SMI_STS2 register; these
status bits are not cleared by a write of ‘1’. The SMI logic for these events is implemented such that each event is
directly combined with the corresponding enable bit in order to generate an SMI.
See the “Runtime Registers” section for the definition of these registers.
SMSC LPC47S45x
Page 154 of 259
Rev. 06-01-06
DATASHEET