LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 4

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

SMSC LPC47S45x
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.7.7
6.8.1
6.8.2
6.8.3
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.9.6
6.9.7
6.9.8
6.9.9
6.10.1
6.10.2
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
6.11.6
6.11.7
6.11.8
6.11.9
6.11.10
6.12.1
6.12.2
6.12.3
6.12.4
6.12.5
6.12.6
6.12.7
6.14.1
6.14.2
6.15.1
6.15.2
6.16.1
6.16.2
6.17.1
6.17.2
6.18.1
6.18.2
6.18.3
6.18.4
6.18.5
6.18.6
6.18.7
6.18.8
6.18.9
6.18.10
6.19.1
6.19.2
P
R
OWER
EAL
S
8042 K
G
W
P
F
D
SMB
SMB
X-B
AN
ERIAL
OWER
EVICE
ENERAL
ATCH
Parallel Port Floppy Disk Controller ........................................................................................................92
FDC Power Management .......................................................................................................................94
UART Power Management.....................................................................................................................96
Parallel Port ............................................................................................................................................96
Configuration Registers ..........................................................................................................................97
Host I/O Interface....................................................................................................................................98
Internal Registers....................................................................................................................................98
Time Calendar and Alarm.......................................................................................................................99
Update Cycle ........................................................................................................................................100
Control and Status Registers ................................................................................................................100
Interrupts ..............................................................................................................................................103
32kHz Clock Input.................................................................................................................................104
Power Management..............................................................................................................................104
T
US
S
IME
Timing Diagrams For SER_IRQ Cycle ..............................................................................................105
Routable IRQ To Serial IRQ Conversion Capability ..........................................................................107
Keyboard Interface............................................................................................................................108
External Keyboard and Mouse Interface ...........................................................................................109
Keyboard Power Management..........................................................................................................110
Interrupts ...........................................................................................................................................110
Memory Configurations .....................................................................................................................110
Register Definitions ...........................................................................................................................110
External Clock Signal ........................................................................................................................111
Default Reset Conditions ..................................................................................................................111
Latches On Keyboard and Mouse IRQs............................................................................................113
Keyboard and Mouse PME Generation.............................................................................................114
GPIO Pins .........................................................................................................................................115
Description ........................................................................................................................................116
GPIO Control.....................................................................................................................................118
GPIO Operation ................................................................................................................................119
GPIO PME and SMI Functionality .....................................................................................................120
Either Edge Triggered Interrupts .......................................................................................................121
LED Functionality ..............................................................................................................................122
VCC Power on Elapsed Time Counter..............................................................................................123
VTR Power on Elapsed Time Counter ..............................................................................................123
Fan Speed Control ............................................................................................................................124
Fan Speed Monitoring.......................................................................................................................125
Device Disable Register (LPC only) ..................................................................................................128
SMBus2 Device Disable Register (SMBus2 only) .............................................................................128
Configuration Registers.....................................................................................................................129
Runtime Registers.............................................................................................................................129
SMBus Protocols supported by SMBus2 ..........................................................................................136
Command Codes ..............................................................................................................................136
X-Bus SMBus2/LPC Arbitration.........................................................................................................137
SMBus2 Register Summary ..............................................................................................................139
SMBus2 Register Description ...........................................................................................................139
Invalid Command Protocol Response Behavior ................................................................................141
Slave Device Time-Out .....................................................................................................................142
Stretching the SCLK Signal...............................................................................................................142
SMBus Timing...................................................................................................................................142
Bus Reset Sequence ........................................................................................................................142
I/O Cycles .........................................................................................................................................143
Supported LCD Controllers ...............................................................................................................146
US
US
M
PEED
I
EYBOARD
ANAGEMENT
IRQ................................................................................................................................................105
2 S
NTERFACE
D
O
D
C
C
OG
ISABLE
N
P
ONTROLLER
LOCK
LAVE
URPOSE
E
C
T
LAPSED
ONTROL
IMER
............................................................................................................................................97
R
D
C
.......................................................................................................................................143
EVICE
EGISTER
ONTROLLER
.....................................................................................................................................122
......................................................................................................................................94
I/O...............................................................................................................................115
T
A
.................................................................................................................................129
IMER
ND
..............................................................................................................................135
M
..........................................................................................................................128
(POET)............................................................................................................123
ONITORING
D
ESCRIPTION
DATASHEET
.......................................................................................................124
Page 4 of 259
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Rev. 06-01-06