LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 112

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal
is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software
means of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller.
Writing a 1 to bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6µs, after a delay of a
minimum of 14µs. Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset
of a write to Port 92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0).
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port
92 Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is output on pin KRESET
and its polarity is controlled by the GPI/O polarity configuration.
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible
software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to
control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low
drives nA20M to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92
Register forces ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE
from the keyboard controller. Upon reset, this signal is driven low.
SMSC LPC47S45x
BIT
0
Alternate System Reset. This read/write bit provides an alternate system reset function. This function
provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual
Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by the
Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the
nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of 500 ns. Before another
nALT_RST pulse can be generated, this bit must be written back to a 0.
Note: When Port 92 is disabled,
writes are ignored and reads
return undefined values.
P92
8042
Bit 0
P20
8042
P21
Pulse
0
0
1
1
Gen
14us
KRST_GA20
DATASHEET
Bit 2
PORT 92 REGISTER
nGATEA20
Page 112 of 259
ALT_A20
6us
14us
0
1
0
1
FUNCTION
KRST
6us
nALT_RST
System
nA20M
0
1
1
1
KBDRST
Rev. 06-01-06