LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 37
![no-image](/images/no-image-200.jpg)
LPC47S457-NC
Manufacturer Part Number
LPC47S457-NC
Description
Advanced I/O with X-Bus Interface
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LPC47S457-NC.pdf
(259 pages)
- Current page: 37 of 259
- Download datasheet (2Mb)
PS/2 Mode
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are
selected.
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data
rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a PCI reset.
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
Model 30 Mode
BITS 0 - 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data
rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a PCI reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 - 6 UNDEFINED
Always read as a logic "0"
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
SMSC DS – LPC47S45x
RESET
COND.
RESET
COND.
CHG
CHG
DSK
DSK
N/A
N/A
7
7
N/A
0
6
0
6
1
DATASHEET
N/A
0
5
0
5
1
Page 37 of 259
N/A
4
0
0
4
1
DMAEN NOPREC DRATE
N/A
3
0
3
1
DRATE
SEL1
N/A
2
2
0
DRATE
SEL0
N/A
SEL1
1
1
1
nDENS
nHIGH
DRATE
SEL0
0
1
0
0
Rev. 07/09/2001
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