LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 135

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

The SMBus master/slave controller does not implement hardware to release the clock/data lines upon detecting a
timeout that exceeds the T
master or slave can hold the SMBus indefinitely and the slave can respond improperly following a timeout, thereby
restricting access to the SMBus by other devices on the bus. Software can issue a stop on the SMBus, or reset the
master/slave controller by setting the SMB_RST bit. This can be done based on polling the TE bit or enabling
interrupts based on SMBus timeout error.
Sample Transaction Diagram
The following figure illustrates a data transaction on the SMBus.
6.18 SMBus2 Slave Device
The LPC47S45x is equipped with two independent SMBus devices each with its own slave address that share the
SCLK and SDAT pins. The first device, described in the previous section, is a master/slave controller and is referred
to in this document as the SMBus. The second device, referred to as SMBus2, is a slave only device used to access
internal SMBus2 Registers and the I/O devices on the X-Bus.
The SMBus2 controller will maintain its slave address in the Runtime Register block at offset 0x76. The SMBus2
slave device has four possible bootable addresses by using the strapping options, SADR0 and SADR1, located on
pins 101 and 103. Both the SMBus and SMBus2 have programmable slave addresses since they reside in read/write
registers. In addition, since each of these devices have their own SMBus address, there is no need to provide any
extra control signals between the two devices.
Note: The SMBus2 controller is running at boot-up and may be accessed even if the processor fails. This allows the
the system designer the ability to communicate with peripheral devices attached to the X-Bus from an external host
controller. (i.e. the LCD controller, the Com 2 port, etc.).
The SMBus and the LPC interface both access the X-Bus, therefore arbitration registers have been provided. The
grant bit in these registers reflects the state of the logic that gives either bus control of the X-Bus. See section 6.18.3
X-Bus SMBus2/LPC Arbitration on page 137.
SMSC LPC47S45x
SMB Data
SMB Clk
Start
LPC47S45x
FIGURE 8 − REPRESENTATIVE DIAGRAM OF SMBUS AND SMBUS2
(SMBus2)
(SMBus)
Master/
Slave
Slave
TIMEOUT
FIGURE 7 − SAMPLE SMBUS SINGLE BYTE TRANSACTION
0
value shown in the Timing Diagrams Section for the SMBus timing. The SMBus
1
DATASHEET
0
Send Address / Byte
SCLK
SDAT
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1
SMBus
1
device
0
SMBus
device
1
Host Controller
0
SMBus
Ack
Rev. 06-01-06