LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 144

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

Chip Selects
The LPC47S45x performs 16-bit address qualification on the X-Bus base I/O addresses. That is, the upper 4-bits,
bits[15:12], must be ‘0’. Note: Bit 6 of the OSC Global Configuration Register (CR24) must be set to ‘1’ for 16-bit
address qualification.
Note: The four LSB of the Address (or Command Code) are always forwarded to the address signals XA[3:0],
regardless of what mode is programmed in the X-Bus Selection Configuration Register.
nXCS0
Chip select zero is activated only if the I/O address bits 12 to 15 are zero and bits 0 to 11 match the Base I/O
Address, which is stored in Logical device 8 at offsets 60h and 61h.
XCS1
Chip select one is activated only if the I/O address bits 12 to 15 are zero and bits 2 to 11 match the Base I/O
Address, which is stored in Logical device 8 at offsets 62h and 63h.
nXCS2 and nXCS3
Activation of chip selects two and three are dependent on the Mode of Operation selected. See below.
Modes of Operation
This interface has been designed to operate in two modes of operation. Both modes offer 4 separte chip selects
(nXCS0 – nXCS3), a read strobe (nXRD), a write strobe (nXWR) and an 8 bit data bus (XD0 – XD7). External
pullups are required on the nXRD and nXWR pins.
The mode of operation determines the number of bits in the base I/O addresses required to activate nXCS2 and
nXCS3. The mode is chosen via bit 0 of the X-Bus Selection Configuration Register located in Logical Device 8 at
0xF0.
See FIGURE 11 for a representative diagram of the operation of the X-Bus interface in both Modes 1 and 2. Notice
that nXCS0 and XCS1 operate the same in Modes one and two.
X-Bus Chip Select Base I/O Address Registers
The Base I/O Address Registers for the X-bus are defined in the Configuration section. See Table 93 − X-Bus,
Logical Device 8 [Logical Device Number = 0x08] on page 185.
X-Bus I/O Configuration Register
X-Bus Selection Register is used to select the X-bus mode and the pulse widths of the X-bus read and write strobes.
This register is located in Logical Device 8 at an offset of 0xF0. See the Configuration section for register description.
See the “Timing Diagrams” section for figures that show “representative” LPC I/O to X-bus cycle timing.
SMSC LPC47S45x
In X-Bus Mode 1, the X-bus base I/O address configuration registers for nXCS2 and nXCS3 contain address bits
A15 through A8 and A7 through A2, respectively. A1 and A0 pass directly through to XA1 and XA0, respectively.
The chip selects only become active for the LPC bus cycle in which the address match occurs.
In X-Bus Mode 2, the X-bus base I/O address configuration registers for nXCS2 and nXCS3 contain address bits
A15 through A8 and A7 through A4, respectively. A3, A2, A1 and A0 pass directly through to XA3, XA2, XA1
and XA0, respectively. The chip selects only become active for the LPC bus cycle in which the address match
occurs.
DATASHEET
Page 144 of 259
Rev. 06-01-06