LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 203

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

Note 1: A logical device will be active and powered up according to the following equation:
Note 2: If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical Device I/O
Note 3: The default value of the Primary Interrupt Select register for logical device 0 is 0x06.
Note 4: The DMA (0x74) default address for logical device 0 (FDD) is 0x02 and for logical device 3 is 0x04.
Note 5: The default values for the Primary Base I/O Address Register for logical device 0 (FDD) are 0x60=0x03 and
SMSC LPC47S45x
DMA Channel Select
Default = 0x02 or 0x04
(Note 4)
on VCC POR, VTR POR,
PCI RESET and
SOFT RESET
32-Bit Memory Space
Configuration
Logical Device
Logical Device
Configuration
Reserved
LOGICAL
NUMBER
DEVICE
LOGICAL DEVICE
0x00
0x01
0x02
0x03
REGISTER
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or
clears the other.
map, then read or write is not valid and is ignored.
0x61=0xF0.
LOGICAL
Reserved
Reserved
DEVICE
Parallel
FDC
Port
Table 84 − I/O Base Address Configuration Register Description
(0xA9-0xDF)
(0xE0-0xFE)
(0x76-0xA8)
(0x74,0x75)
ADDRESS
REGISTER
0xFF
0x60,0x61
0x60,0x61
INDEX
n/a
n/a
Table 83 − Logical Device Registers
Only 0x74 is implemented for FDC and Parallel port. 0x75 is
not implemented and ignores writes and returns zero when
read.
description.
Reserved - not implemented. These register locations ignore
writes and return zero when read.
Reserved - not implemented. These register locations ignore
writes and return zero when read.
Reserved - Vendor Defined (see SMSC defined Logical Device
Configuration Registers).
Reserved
DATASHEET
EPP is only available when
the base address is on an
(all modes supported,
on 8-byte boundaries
on 4-byte boundaries
on 8-byte boundaries
(EPP Not supported)
Refer to DMA Channel Select Configuration register
[0x0100:0x0FFC]
[0x0100:0x0FF8]
[0x0100:0x0FF8]
8-byte boundary)
Page 203 of 259
BASE I/O
(Note 1)
RANGE
n/a
n/a
or
DESCRIPTION
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TDR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
n/a
n/a
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h : cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
BASE OFFSETS
FIXED
Rev. 06-01-06
STATE
C
C
C
C