LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 216
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LPC47S457-NC
Manufacturer Part Number
LPC47S457-NC
Description
Advanced I/O with X-Bus Interface
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LPC47S457-NC.pdf
(259 pages)
- Current page: 216 of 259
- Download datasheet (2Mb)
Note 1: If the I/O Base Address of the logical device is not within the Base I/O range as shown in the Logical Device I/O
map, then read or write is not valid and is ignored.
SMSC LPC47S45x
Base I/O Address 3 –
Low Byte (Note 1)
Default = 0x00
on VTR POR, VCC
POR, PCI Reset and
Soft Reset
Bit 1 is reset on
VCC POR, VTR POR
and PCI Reset
X-Bus Selection
Default = 0x0C
on VTR POR
Bit 7 is reset on
VCC POR, VTR POR
and PCI Reset
NAME
Table 93 − X-Bus, Logical Device 8 [Logical Device Number = 0x08]
R/W,
Read-Only
when the Base
I/O Address 3
– Low Byte
Register
bit[1]=1
REG INDEX
(R/W)
0xF0
0x67
Register 0x67 sets the low byte of the base I/O address for chip
select 3. Bit 1 is the write protect bit for registers 66 and 67.
Bit 0 is the disable bit for nXCS3.
Mode 1:
Bits [7:2] =address[7:2]
Mode 2:
Bits [7:4] =address[7:4]
Bits [3:2] are reserved
Bit[1] = Register 66, 67 Write Protect. Cleared by VCC POR,
VTR POR, and PCI Reset only. Cannot be cleared by software
writing to this bit.
0=Register 66 and 67 are read/write
1=Register 66 and 67 are read-only
Bit[0] = Disable bit for nXCS3.
0=enable chip select
1=disable chip select
Bit[0] X-Bus Mode.
0=Mode 1
1=Mode 2
Note that the GPIOs must be configured properly to use the
selected mode. The GPIOs are not automatically configured
for the mode selected.
Bit[1] Reserved
Bits[3:2] X-Bus Read/Write Pulse Width Selection. These bits
select the pulse width of the X-bus read and write strobes.
They extend the LPC cycle accordingly by adding wait states
(sync fields) into the cycle.
11=540nsec min (default)
10=420nsec min
01=300nsec min
00=180nsec min
Bits[6:4] Reserved
Bit[7] Register Write Protect. Cleared by VCC POR, VTR POR
and PCI Reset only. Cannot be cleared by software writing this
bit.
0=X-Bus selection register is Read/Write.
1=X-Bus Selection register is Read-Only
DATASHEET
Page 216 of 259
DEFINITION
Rev. 06-01-06
STATE
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