LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 23

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

Note: GP70 to GP77 and GP80 to GP87 are VCC powered I/O pins. They cannot be used for wake-up.
Note: The LPC, X-Bus, SMBus, and SMBus2 interface pins are powered by VCC and cannot be used for wake-up.
5.8 40MHz Clock Output
The LPC47S45X offers a 40.5430160 MHz clock output signal at pin 128, referred to as CLKO40. This 40MHz clock
source is taken from either the external 32kHz clock source or from the internally derived 32 kHz signal from the
14MHz clock source. The frequency stability of the 40MHz output is ±200ppm, max. This 40MHz clock output is
powered by VTR and is active (running) following a VTR POR. This clock operates at a 50% duty cycle ±20% (i.e.
60/40 or 40/60 duty cycle).
This 40MHz clock output can be turned on or off by a bit in a register. This bit is located at Bit[2] of the Clock Select
register at 0xF0 in Logical Device A and is referred to as CLKO40_PWR. This register is powered by VTR and reset
on a VTR POR.
Bit[2] (CLKO40_PWR) is defined as follows:
0 = 40MHz clock output is on (default)
1 = 40MHz clock output is off
5.9 Maximum Current Values
See the “Operational Description” section for the maximum current values.
The maximum VTR current, I
3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin
that is driven by VTR. The pins that are powered by VTR include the following: GP42/IO_PME#, GP53/TXD2/IRTX,
GP60/LED1, GP61/LED2. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V
when driving.
The maximum VCC current, I
3.3V).
The maximum Vbat current, I
3.3V).
5.10 Power Management Events (PME/SCI)
The LPC47S45x offers support for Power Management Events (PMEs), also referred to as System Control Interrupt
(SCI) events. The terms PME event and SCI event refer to the indication of an event to the chipset via the assertion
of the nIO_PME output signal on pin 20.
PME events are caused by a status bit being set in the PME status registers. These enabled PME events will only
generate an IO_PME# signal if the PME_En bit is set in the PME_EN register at offset 02h in the Runtime Register
block. SCI events are caused by a status bit being set in the PM1 or GPE status registers. These registers are ACPI
SMSC DS – LPC47S45x
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Other Pins
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nRI1 (input)
GP50/nRI2 (input)
GP52/RXD2/IRRX (input)
KDAT (input)
MDAT (input)
nPB_IN
GPIOs (GP10-GP17, GP20-GP27, GP30-GP37, GP41, GP43, GP50-GP57, GP60, GP61) – all input-only
except GP53, GP60, GP61. See below.
GP53/TXD2/IRTX (output, buffer powered by VTR)
GP60/LED1 (output, buffer powered by VTR)
GP61/LED2 (output, buffer powered by VTR
CLKO40 (output, buffer powered by VTR))
nPS_ON (output, buffer powered by VTR))
BAT
TR
CC
, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or
, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or
, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or
DATASHEET
Page 23 of 259
Rev. 07/09/2001