LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 159
![no-image](/images/no-image-200.jpg)
LPC47S457-NC
Manufacturer Part Number
LPC47S457-NC
Description
Advanced I/O with X-Bus Interface
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LPC47S457-NC.pdf
(259 pages)
- Current page: 159 of 259
- Download datasheet (2Mb)
Note:
Note 1:
Note 2:
Note 3:
when bit 1 of the Device Disable Register is ‘1’.
Note 4:
at power-up.
Note 4a: Bit [3] of this register is reset (cleared) on VCC POR and PCI Reset (and VTR POR) for TXD2/IRTX output
default at power-up.
Note 5:
Note 6:
is activated, PINT follows the nACK input.
Note 7:
Note 7a: This register is powered by VTR and Vbat. It is reset on Vbat POR to a default value of 0x00 and Bit[7] is
cleared on a VTR POR
Note 8:
the current state of the arbitration logic.
Note 9: The two LSBs of the VTR POR reset value of the SMBus2 slave address and enable register are
determined by the state of the strapping option pins, SADR0 and SADR1, following a VTR power-on-reset.
Note 10: Bits[7:0] may be individually reset on Vcc Reset, PCI Reset, and VTR POR if enabled in Logical Device A at
offset 0xF6.
Note 11: Bit[1] is set/reset by the arbitration logic and Read only by the LPC Bus.
SMSC LPC47S45x
OFFSET
(hex)
7C
7D
7A
7B
7E
7F
Reserved bits return 0 on read.
This register contains some bits that are read or write only.
Bit 0 is not cleared by PCI RESET.
The Device Disable Register is read-only when GP43 register bit [3:2] = 01 AND the GP43 pin is high, or
Bit [3] of this register is reset (cleared) on VCC POR and PCI Reset (and VTR POR) for fan output default
Bits [3:2] of the GP43 register are reset (cleared) on VCC POR and PCI Reset (and VTR POR).
The parallel port interrupt defaults to 1 when the parallel port activate bit is cleared. When the parallel port
This register is powered by VTR and Vbat. It is reset on Vbat POR to a default value of 0x00
A soft reset only resets Bit[0] (LPC_REQ) of the LPC_ARB Arbitration Register. Bit[1] will always reflect
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
RESET
PCI
-
-
-
-
-
-
POR
VCC
-
-
-
-
-
DATASHEET
(Note 7)
(Note 7)
POR
0x00
0x00
VTR
-
-
Page 159 of 259
Vbat
POR
0x00
0x00
0x00
0x00
-
-
RESET
SOFT
-
-
-
-
-
-
PM1_EN1
PM1_EN2
GPE1_STS 1
GPE1_STS 2
GPE1_EN 1
GPE1_EN 2
REGISTER
Rev. 06-01-06
SMBus2
OFFSET
REG
-
-
-
-
-
-
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