PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 88

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

FALC56 V1.2
PEB 2256
Functional Description E1
S
6-Bit Error Indication Counters
a
The S
6-bit error indication counter CRC2L/H (16 bits) counts the received S
6-bit
a
a
sequence 0001 or 0011 in every CRC submultiframe. In the primary rate access digital
section this counter option gives information about CRC errors reported from the TE by
the S
6 bit. Incrementing is only possible in the multiframe synchronous state. The S
6-
a
a
bit error indication counter CRC3L/H (16 bits) counts the received S
6-bit sequence
a
0010 or 0011 in every CRC submultiframe. In the primary rate access digital section this
counter option gives information about CRC errors detected at T-reference point and
reporting them by the S
6-bit. Incrementing is only possible in the multiframe
a
synchronous state.
4.2.3.8
E-Bit Access (E1)
Due to signaling requirements, the E-bits of frame 13 and frame 15 of the CRC
multiframe can be used to indicate received errored submultiframes:
Submultiframe I statusE-bit located in frame 13
Submultiframe II statusE-bit located in frame 15
no CRC error: E = 1; CRC error:E = 0
Standard Procedure
After reading the submultiframe error indication RSP.SI1 and RSP.SI2, the
microprocessor has to update the contents of register XSP (XS13, XS15). Access to
these registers has to be synchronized on transmit or receive multiframe begin interrupts
(ISR0.RMB or ISR1.XMB).
Automatic Mode
In the multiframe synchronous state the E-bits are processed according to ITU-T G.704
independently of bit XSP.EBP (E-bit polarity selection).
By setting bit XSP.AXS status information of received submultiframes is automatically
inserted in the E-bit position of the outgoing CRC multiframe without any further
interventions of the microprocessor.
In the doubleframe and multiframe asynchronous state the E-bits are set or cleared,
depending on the setting of bit XSP.EBP.
Submultiframe Error Indication Counter
The EBC (E-Bit) counter EBCL/H (16 bits) counts zeros in the E-bit position of frame 13
and 15 of every received CRC multiframe. This counter option gives information about
the outgoing transmit PCM line if the E-bits are used by the remote end for submultiframe
error indication. Incrementing is only possible in the multiframe synchronous state.
Data Sheet
88
2002-08-27