PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 268

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PEB2256E

Manufacturer Part Number
PEB2256E
Description
E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
Port Configuration 6 (Read/Write)
Value after reset: 00
PC6
SXCL(1:0)
SCL(2:0)
Data Sheet
7
Select Transmit Clock Frequency on Port CLK2
Port CLK2 is the de-jittered DCO-X clock at a frequency of
00 = 2.048 MHz
01 = 4.096 MHz
10 = 8.192 MHz
11 = 16.384 MHz
Select System Clock Frequency on Port CLK1
Port CLK1 is the de-jittered DCO-R clock at a frequency of
000 = 8 kHz
001 = 2.048 MHz
010 = 4.096 MHz
011 = 8.192 MHz
100 = 16.384 MHz
101 to 111 = Not defined
Note: If DCO-R is not active, no clock is output on pin CLK1
Note: If DCO-X is not used, no clock is output on pin CLK2
H
(SIC1.RBS(1:0)=11 and CMR1.RS1=0).
(SIC1.XBS(1:0)=00 and CMR1.DXJA=1; buffer bypass and
no jitter attenuation)
SXCL1
268
SXCL0
SCL2
SCL1
SCL0
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(86)

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