PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 206

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

HDLC mode is selected, the limits for “Valid Frame” check are modified (refer to
description of bit RSIS.VFR).
• Transmit Direction
If CCR2.XCRC is set, the CRC checksum is not generated internally. The checksum has
to be provided via the transmit FIFO (XFIFO) as the last two bytes. The transmitted frame
is closed automatically by a closing flag only.
The FALC56 does not check whether the length of the frame, i.e. the number of bytes to
be transmitted is valid or not.
8.3.3
The address field of received frames can be pushed to the receive FIFOs (first one or
two bytes of a frame). This function is used together with extended address recognition.
It is enabled by setting control bit CCR2.RADD (CCR3.RADD2, CCR4.RADD3).
8.3.4
In transmit direction 2
checking the XFIFO status by polling bit SIS.XFW (SIS2.XFW2, SIS3,XFW3) or after an
interrupt ISR1.XPR (ISR5.XPR2, ISR5.XPR3, Transmit Pool Ready), up to 32 bytes can
be entered by the CPU to the XFIFOs.
The transmission of a frame can be started by issuing a XTF or XHF command via the
command registers. If the transmit command does not include an end of message
indication (CMDR.XME, CMDR3.XME2, CMDR4.XME3), the FALC56 will repeatedly
request for the next data block by means of an XPR interrupt as soon as no more than
32 bytes are stored in the XFIFO, i.e. a 32-byte pool is accessible to the CPU.
This process is repeated until the CPU indicates the end of message by XME command,
after which frame transmission is finished correctly by appending the CRC and closing
flag sequence. Consecutive frames can share a flag, or can be transmitted as back-to-
back frames, if service of the XFIFOs is fast enough.
In case no more data is available in the XFIFOs prior to the arrival of XME, the
transmission of the frame is terminated with an abort sequence and the CPU is notified
by interrupt ISR1.XDU (ISR4.XDU2, ISR5.XDU3). The frame can be aborted by software
using CMDR.SRES (CMDR3.SRES2, CMDR4.SRES3).
The data transmission sequence, from the CPU’s point of view, is outlined in
Data Sheet
Receive Address Pushed to RFIFO
HDLC Data Transmission
32 byte FIFO buffers are provided for each HDLC channel. After
206
Signaling Controller Operating Modes
FALC56 V1.2
PEB 2256
Figure
2002-08-27
78.