PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 118

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

4.6.6
Alarm simulation does not affect the normal operation of the device, i.e. all time slots
remain available for transmission. However, possible
reported to the processor or to the remote end when the device is in the alarm simulation
mode.
The alarm simulation is initiated by setting the bit FMR0.SIM. The following alarms are
simulated:
• Loss-Of-Signal (LOS)
• Alarm Indication Signal (AIS)
• Loss of pulse frame
• Remote alarm indication
• Receive and transmit slip indication
• Framing error counter
• Code violation counter (HDB3 Code)
• CRC4 error counter
• E-Bit error counter
• CEC2 counter
• CEC3 counter
Some of the above indications are only simulated if the FALC56 is configured to a mode
where the alarm is applicable (e.g. no CRC4 error simulation when doubleframe format
is enabled).
Setting of the bit FMR0.SIM initiates alarm simulation, interrupt status bits are set. Error
counting and indication occurs while this bit is set. After it is reset all simulated error
conditions disappear, but the generated interrupt statuses are still pending until the
corresponding interrupt status register is read. Alarms like AIS and LOS are cleared
automatically. Interrupt status registers and error counters are automatically cleared on
read.
4.6.7
Single bit defects can be inserted into the transmit data stream for the following
functions:
FAS defect, multiframe defect, CRC defect, CAS defect, PRBS defect and bipolar
violation.
Defect insertion is controlled by register IERR.
Data Sheet
Alarm Simulation (E1)
Single Bit Defect Insertion
118
real
Functional Description E1
alarm conditions are not
FALC56 V1.2
PEB 2256
2002-08-27