PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 208

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

8.3.5
2 32 byte FIFO buffers are also provided in receive direction for each HDLC channel.
There are different interrupt indications concerned with the reception of data:
• RPF (RPF2, RPF3, receive pool full) interrupt, indicating that a 32-byte block of data
• RME (RME2, RME3, receive message end) interrupt, indicating that the reception of
The following figure gives an example of a reception sequence, assuming that a “long”
frame (66 bytes) followed by two short frames (6 bytes each) are received.
Figure 80
8.3.6
The FALC56 supports the S
• Access via registers RSW/XSW
• Access via registers RSA(8:4)/XSA(8:4)
• Access via the 64 byte deep receive/transmit FIFO of the integrated signaling
Data Sheet
can be read from RFIFO (RFIFO2, RFIFO3) and the received message is not yet
complete.
one message is completed.
capable of storing the information for a complete multiframe
controller (HDLC channel 1 only). This S
receive a transparent bit stream as well as HDLC frames where the signaling
controller automatically processes the HDLC protocol. Enabling is done by setting of
bit CCR1.EITS and resetting of registers TTR(4:1), RTR(4:1) and FMR1.ENSA.
FALC
System
Interface
CPU
Interface
R
Receive Frame 1 (66 bytes)
32
HDLC Data Reception
S
RPF
a
-bit Access (E1)
Interrupt Driven Reception Sequence Example
RD RFIFO
32 bytes
32
RMC
RPF
a
2
-bit signaling of time slot 0 of every other frame as follows:
RF2 RF3
6
RD RFIFO
32 bytes
6
RMC
208
a
RME
-bit access gives the opportunity to transmit/
Signaling Controller Operating Modes
RMC
RME
RMC
RME
FALC56 V1.2
PEB 2256
2002-08-27
ITD10972
RMC