PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 382

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Errored Second Mask (Read/Write)
Value after reset: FF
ESM
ESM
Disable Error Counter (Write)
Value after reset: 00
DEC
DRBD
DCOEC
DBEC
DCEC
DEBC
DCVC
DFEC
Note: Error counters and receive buffer delay can be read 1 µs after setting the
Data Sheet
according bit in bit DEC.
DRBD
LFA
7
7
Errored Second Mask
This register functions as an additional mask register for the interrupt
status bit Errored Second (ISR3.ES). A "1" in a bit position of ESM
deactivates the related second interrupt.
Disable Receive Buffer Delay
This bit has to be set before reading the register RBD. It is
automatically reset if RBD has been read.
Disable COFA Event Counter
Disable PRBS Bit Error Counter
Only valid if LCR1.EPRM = 1 and FMR1.ECM are reset.
Disable CRC Error Counter
Disable Errored Block Counter
Disable Code Violation Counter
Disable Framing Error Counter
These bits are only valid if FMR1.ECM is cleared. They have to be set
before reading the error counters. They are reset automatically if the
corresponding error counter high byte has been read. With the rising
edge of these bits the error counters are latched and then cleared.
FER
H
H
DCOEC
CER
DBEC
AIS
382
DCEC
LOS
DEBC
CVE
DCVC
SLIP
T1/J1 Registers
DFEC
FALC56 V1.2
0
0
PEB 2256
2002-08-27
(47)
(60)