PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 258

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Clock Mode Register 1 (Read/Write)
Value after reset: 00
CMR1
RS(1:0)
DCS
STF
DXJA
Data Sheet
7
Select RCLK Source
These bits select the source of RCLK.
00 = Clock recovered from the line through the DPLL drives RCLK
01 = Clock recovered from the line through the DPLL drives RCLK
10 = Clock recovered from the line is de-jittered by DCO-R to drive a
11 = Clock recovered from the line is de-jittered by DCO-R to drive a
Disable Clock-Switching
In Slave mode (LIM0.MAS = 0) the DCO-R is synchronized on the
recovered route clock. In case of loss-of-signal LOS the DCO-R
switches automatically to the clock sourced by port SYNC. Setting
this bit automatic switching from RCLK to SYNC is disabled.
Select TCLK Frequency
Only applicable if the pin function TCLK port XP(A to D) is selected by
PC(4:1).XPC(3:0) = 0011
clocked with TCLK.
0 =
1 =
Disable Internal Transmit Jitter Attenuation
Setting this bit disables the transmit jitter attenuation. Reading the
data out of the transmit elastic buffer and transmitting on XL1/2
(XDOP/N/XOID) is done with the clock provided on pin TCLK. In
transmit elastic buffer bypass mode the transmit clock is taken from
SCLKX, independent of this bit.
H
and in case of an active LOS alarm RCLK pin is set high.
2.048 MHz clock on RCLK.
8.192 MHz clock on RCLK.
2.048 MHz
8.192 MHz
RS1
RS0
258
B
. Data on XL1/2 (XDOP/N / XOID) are
DCS
STF
DXJA
DXSS
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(44)