PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 190

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 46
Register
RAH(2:1)
RAL(2:1)
GCM(6:1)
E1 Initialization
For a correct start up of the primary access interface a set of parameters specific to the
system and hardware environment must be programmed after reset goes inactive. Both
the basic and the operational parameters must be programmed before the activation
procedure of the PCM line starts. Such procedures are specified in ITU-T and ETSI
recommendations (e.g. fault conditions and consequent actions). Setting optional
parameters primarily makes sense when basic operation via the PCM line is guaranteed.
Table 47
control bits which are to be programmed in one of the above steps. The sequence is
recommended but not mandatory. Accordingly, parameters for the basic and operational
set up, for example, can be programmed simultaneously. The bit FMR1.PMOD should
always be kept low (otherwise T1/J1 mode is selected).
Table 47
Basic Set Up
Master clocking mode
E1 mode select
Specification of line interface and clock
generation
Line interface coding
Loss-of-signal detection/recovery
conditions
System clocking and data rate
Transmit offset counters
Receive offset counters
AIS to system interface
Data Sheet
gives an overview of the most important parameters in terms of signals and
Reset Value Meaning
FD
FF
all 00
Initial Values after Reset (E1) (cont’d)
Initialization Parameters (E1)
H
H
, FF
, FF
H
H
H
Compare register for receive address cleared
Fixed clock mode selected (2.048 MHz on pin MCLK
required).
190
GCM(6:1) according to external MCLK
clock frequency
FMR1.PMOD = 0
LIM0, LIM1, XPM(2:0)
FMR0.XC(1:0), FMR0.RC(1:0)
PCD, PCR, LIM1, LIM2
SIC1.SSCC(1:0),
SIC1.SSD1,FMR1.SSD0
CMR2.IRSP/IRSC/IXSP/IXSC
XC0.XCO, XC1.XTO
RC0.RCO, RC1.RTO
FMR2.DAIS/SAIS
Operational Description E1
FALC56 V1.2
PEB 2256
2002-08-27