PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 34

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 2
Pin
No.
7
Data Sheet
Ball
No.
D4
Pin Definitions - Line Interface (cont’d)
Symbol
XL1
XDOP
XOID
Input (I)
Output (O)
Supply (S)
O (analog) Transmit Line 1
O
O
Line Interface Transmit
Function
Analog output to the external transformer.
Selected if LIM1.DRS is cleared. After reset
this pin is in high-impedance state until bit
FMR0.XC1 is set and XPM2.XLT is cleared.
Transmit Data Output Positive
This digital output for transmitted dual-rail
PCM(+) route signals can provide
- half bauded signals with 50% duty cycle
(LIM0.XFB = 0) or
- full bauded signals with 100% duty cycle
(LIM0.XFB = 1)
The data is clocked with positive transitions of
XCLK in both cases. Output polarity is selected
by bit LIM0.XDOS (after reset: active low). The
dual-rail mode is selected if LIM1.DRS and
FMR0.XC1 are set. After reset this pin is in
high-impedance state until register LIM1.DRS
is set and XPM2.XLT is cleared.
Transmit Optical Interface Data
Unipolar data sent to a fiber-optical interface
with 2048 kbit/s (E1) or 1544 kbit/s (T1/J1)
which is clocked on the positive transitions of
XCLK. Clocking of data in NRZ code is done
with 100% duty cycle. Data in CMI code is
shifted out with 50% or 100% duty cycle on
both transitions of XCLK according to the CMI
coding. Output polarity is selected by bit
LIM0.XDOS (after reset: data is sent active
high).
The single-rail mode is selected if LIM1.DRS is
set and FMR0.XC1 is cleared. After reset this
pin is in high-impedance state until register
LIM1.DRS is set and XPM2.XLT is cleared.
34
Pin Descriptions
FALC56 V1.2
PEB 2256
2002-08-27